Work Experience

2005.7 - Present
IC Development Engineer
NXP Semiconductors (Former Philips Semiconductor), BL Cellular Systems, MST Baseband - Shanghai, China

  • Currently developing a digital baseband chip containing ARM946 and R.E.A.L DSP. The chip will be fabricated in a 90nm process with the first tape-out in December, 2006.
  • Responsible for the entire design synthesis flow, netlist screening and formal verification.
  • Writing timing constraints for system-controller subsystem, DSP subsystem and DFT and responsible for timing sign-off.
  • Participated in PNX6511 risk assessment and tracking.
  • Integrated DSP Firmcore into design database and updated corresponding testcases.
  • Responsible for DSP supplier agreement management.
  • Developed an ARM7 based digital baseband chip from July 2005 to January 2006. The project was stopped due to business reason.
  • Translated timing constraints from PKS TCL to SDC and verified the constraints.
  • Set up clock tree synthesis flow and wrote clock tree synthesis constraints.
  • Set up PrimeTime environment and performed static timing analysis.
  • Received training in backend design in Zurich, Switzerland.

04/2002.4 - 06/2005
Technical Support Engineer
Shanghai Research Center for IC Design, Multi-Project Wafer Department - Shanghai, China

  • Provided customer support for RTL-to-GDS flow.
  • Provided designers with manufacturing support on multiple processes, including CSMC 0.6um DPDM logic, Chartered 0.35um logic/analog/RF and SMIC 0.35um e-EEPROM process.
  • Developed a PIC16C84 compatible MCU, from specification to tape-out. Test chip was fabricated at Chartered 0.35um logic process and first-time right.
  • Participated in multiple customers' design projects. Work packages included synthesis, static timing analysis, RTL coding, FPGA emulation platform set-up and functional verification. Some of the chips are in mass-production.
  • Documented internal digital design flow of CSMC 0.6um logic process and TSMC 0.25um logic process.

Technical Skills

Programming Languages

  • C/C++, Verilog HDL, Perl, C Shell, Korn Shell, Tcl

EDA Tools

  • Synopsys Design Compiler, PrimeTime, Leda
  • Cadence NC-Sim, Ambit BuildGates, RTL Compiler, Silicon Ensemble, Conformal, Dracula DRC
  • Mentor Model-Sim, Calibre DRC

Operating Systems

  • Windows 2000/XP, Solaris, Red Hat Linux