Blog for IC/ASIC/SOC Designtag:blogger.com,1999:blog-57961682006-09-16T13:50:22ZBlogger
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truephilewar2006-09-14T22:21:00+08:002006-09-15T13:04:00Z2006-09-14T14:56:48Ztag:blogger.com,1999:blog-5796168.post-115824580876263104Script to fix random number suffix generated by RC uniquifyIf you are a reader of John Cooley's DeepChip, you must be familiar with the slogan that "It's not a BUG; it's a FEATURE!". Neither do I think it's a bug that RTL Compiler adds five- or six-digit random number suffixes to module names during uniquify and there must be good reasons for C company to do so.
It's fine with me, but not fine with our DfT tool. Our aged DfT tool needs a fixed list offalsephilewar2006-09-12T21:02:00+08:002006-09-12T13:24:55Z2006-09-12T13:24:54Ztag:blogger.com,1999:blog-5796168.post-115806749499646182An Issue Has Been ResolvedIt's quite normal that top semiconductor companies may have their own CAD tools and it's also normal that they may find in-house tools are not as good as those from the Four Big Players. As a result, they start to phase out in-house tools.
Unfortunetely, my project employs one in-house tool that is being phased out and limitedly supported. The tool, I won't disclose its name, will swallow thefalsephilewar2006-03-18T19:46:00+08:002006-03-18T11:53:36Z2006-03-18T11:53:36Ztag:blogger.com,1999:blog-5796168.post-114268281683242040IC design will follow pc-board designThis EDN article describes a law that "everything that happens in IC design, happened in pc-board design many years ago." I quite buy into this idea, because many times I introduce "system on a chip" concept to people, I show them PCB, as the definition of original system.falsephilewar2006-02-07T21:01:00+08:002006-02-07T13:28:19Z2006-02-07T13:28:19Ztag:blogger.com,1999:blog-5796168.post-113931889945231705A Breakthrough in RFIDAn article I read today from eetims talks about Philips has successfully presented a PLASTIC RFID chip. The prototype is at 13.56Mhz, which is said to be a dominant one. Yes, the chips inside our transportation smart card commnuicate with reader at 13.56Mhz.
For myself, once upon a time I was involved a project related to RFID. So I am quite excited by this news.falsephilewar2006-01-30T12:17:00+08:002006-01-30T05:01:28Z2006-01-30T05:01:28Ztag:blogger.com,1999:blog-5796168.post-113859728863524015Happy Chinese New Year!I have not blogged for almost one month, which doesn't mean I stop working on IC Design, :)
In first two weeks of January, we are busy to close our projects. And, max transition violations are recovered and fixed. Then I find it's fixed only in worst case, in best case I have another huge amount of violations. It seems encounter will not fix them automatically. I don't know the reason clearly.falsephilewar2005-12-27T22:09:00+08:002005-12-27T14:36:48Z2005-12-27T14:36:47Ztag:blogger.com,1999:blog-5796168.post-113569420794042903Week 551 and 552 SummaryHappy Holiday! I think we finally achieve a closed timing before year end. When I left office 8PM today, there was only 5 hold violations in functional-mode-best-case-on-chip-variation (10% timing derate). No problems in test mode and in other corners of func mode. Last night I still had 150 hold violation paths in functional-mode-worst-case-on-chip-variation and this morning I found because ptfalsephilewar2005-12-18T20:16:00+08:002005-12-18T13:24:18Z2005-12-18T13:24:18Ztag:blogger.com,1999:blog-5796168.post-113491225809509151Week 550 SummaryOf coz this week we continue playing with place and route, static timing analysis. Last week it was found that timing arc to some output ports can not be reported by SOC Encounter and finally it turns out that encounter disables the timing arc when one pin of pad is tied to high/low. It really sucks. An old version of encounter can report but it crashes during sroute. That's why we upgrade.falsephilewar2005-12-11T21:36:00+08:002005-12-11T14:16:47Z2005-12-11T14:16:47Ztag:blogger.com,1999:blog-5796168.post-113431060736122218Week 549 SummaryI went to company this afternoon and things were still not good. The bottleneck is timing constraints. As you may know, it comes from an old design in PKS tcl mode and I have translated it to sdc. The headache is FE only allows a subset of sdc, e.g. no edge from/to options and no invalid start/end points. -through has been used a lot, which causes other problems coz -through option in false pathsfalsephilewar2005-12-02T21:07:00+08:002005-12-02T13:34:30Z2005-12-02T13:31:16Ztag:blogger.com,1999:blog-5796168.post-113353027691246114Week 548 SummaryOnly four weeks are left ahead of tape-out and timing closure has not been achieved. Things are becoming better and better. We may get some fruits next week. I'm still working on STA. Definitely I learn quite a few of Primetime. As far as I see, setup violation may not be a big trouble but we might be killed by hold violation. Wish PKS could fix!
I wonder whether you know Deepchip.com and Johnfalsephilewar2005-11-26T20:11:00+08:002005-11-26T14:07:42Z2005-11-26T12:32:53Ztag:blogger.com,1999:blog-5796168.post-113300837347855853Week 547 SummaryLast week I talked that my first project was stopped due it was not attractive to market any more. My colleagues and I are still working hard. We target at a tape-out-quality GDS2 end of year and prove that this team is capable of doing very deep sub-micron multi-clock-domain design. The schedule looks a little tight so I go to company this afternoon and work 3 hrs. The job I plan to do today isfalsephilewar2005-11-20T12:08:00+08:002005-11-20T04:18:52Z2005-11-20T04:18:52Ztag:blogger.com,1999:blog-5796168.post-113246033237003909Week 546 SummaryAfter setting up clock tree synthesis, I finish final sta setup this week. Next week I am able to run full chip STA to further debug the quality of my constraints. It seems we are progressive towarding tape-out.
However, Mgmt had a tele-conference with us on Friday. The message was clear that my first project most probably would not be a production. Oh! What a pity! Anyway, it's business and it'sfalsephilewar2005-11-13T20:24:00+08:002005-11-13T12:55:33Z2005-11-13T12:55:33Ztag:blogger.com,1999:blog-5796168.post-113188653384452039Week 545 SummaryI just wonder whether you are bothered or not if I am keeping talking with my routine work. In the past week I was playing with ckSynthesis from Encounter. I have limited experiences on clock tree refinement and also dont know how to evaluate QoR. However, there are some basic principles. I think and perpare to evaluate by STA, which is next week's task.
On Friday I go to Cadence Shanghai tofalsephilewar2005-11-04T23:37:00+08:002005-11-04T15:52:30Z2005-11-04T15:52:30Ztag:blogger.com,1999:blog-5796168.post-113111955045399745Week 544 SummaryThis week I am into clock tree synthesis. As I mentioned last week, I have went through some documents. My job is more or less following the clock tree structure in old design and building one in our new design. As a very novice to encounter, I made stupid mistakes but got it done finally. Before I left office today, I found a big problem that six important clock subtrees are not generated. So Ifalsephilewar2005-10-31T21:39:00+08:002005-10-31T13:44:19Z2005-10-31T13:44:19Ztag:blogger.com,1999:blog-5796168.post-113076625956761168CTS requires a uniquified netlistWhen I try to synthesize a clock tree this afternoon, Encounter refuse with an error message saying:
specifyClockTree Option : -clkfile encounter.cts
**ERROR: CTS requires a uniquified netlist before you can run clock synthesis.
Uniquified? Yes, encounter provide a standalone unix utility "uniquifyNetlist" to do so, and it needs encounter license to do so. Later it seems whenever you do eco, ipofalsephilewar2005-10-29T17:33:00+08:002005-10-29T09:44:34Z2005-10-29T09:44:34Ztag:blogger.com,1999:blog-5796168.post-113057907428000589Week 543 SummaryThis week I have finished timing constraint translation and try getting into clock tree. To do so, I should go through ctpks documents, encounter clock tree synthesis documents and design flow documents. By reading old scripts, I have some ideas how clock tree structure is in wally. Next Monday I can see ctpks log and gain more inside thoughts.
On Thursday my group had an chance to talk to VP HRfalsephilewar2005-10-21T22:31:00+08:002005-10-21T14:49:04Z2005-10-21T14:49:03Ztag:blogger.com,1999:blog-5796168.post-112990614398237187Week 542 SummaryNow I am focusing on static timing analysis. As I have mentioned before, I have to translate PKS tcl scripts to a simple SDC one for encounter, PKS, nanoroute and Primetime. I am fighting all the way to get the right timing report and pads issue arises. So I shift my focus to reporting delay through the pads. I make mistakes and correct them later. I am sitting in front of LCD and thinking. I amfalsephilewar2005-10-14T21:55:00+08:002005-10-14T14:05:34Z2005-10-14T14:05:34Ztag:blogger.com,1999:blog-5796168.post-112929873469134614Week 541 SummaryTiming constraints translation is almost finished. Now I begin to perform timing analysis and ... get a lot of problems. First of all I should clear the issues reported by check_timing. I will work on that topic next week.
Besides all backend design activities, I pass a test for CBIC ISO9001:2000 audit awareness promotion. There are 28 problems in total. Score 23 and above, you pass. At my firstfalsephilewar2005-10-13T21:51:00+08:002005-10-13T14:03:31Z2005-10-13T14:03:31Ztag:blogger.com,1999:blog-5796168.post-112921221192162178New Solvnet Feature - CommandZoneFinally I re-activate my solvnet account. It has been suspended since my former company mail account is deleted(IT guy told me I could keep it as long as I wanted on Friday but I found they deleted it on Monday morning).
Whatever I'm back to Solvnet and find a new feature called CommandZone. It locates in the bottom-right of your browser, still in beta version. CommandZone has two functions. Onefalsephilewar2005-10-07T21:40:00+08:002005-10-07T16:29:21Z2005-10-07T13:49:36Ztag:blogger.com,1999:blog-5796168.post-112869297623121107Week 540 SummaryI only work one day this week and I have fighted with conflicts between synopsys tools and CAD systems most time in the day. Anyway CAD team is so great that they solve all the problems.
I read The Silicon Steamroller from Steve Leibson today and I quite disagree with him. The point is I don't know how he calculate and draw a conculsion that Chinese fabless design companies can already handlefalsephilewar2005-10-04T20:13:00+08:002005-10-04T13:36:46Z2005-10-04T12:53:16Ztag:blogger.com,1999:blog-5796168.post-112843039647942452A funny bugNW's comment reminds me of a funny bug I found recently. I create a huge-period clock in a sdc file and feed it into encounter. Encounter replyes that the value is too large to convert and then it skips clock difinition. I report this problem to inner helpdesk and the expert reproduces the issue both in 4.1 and 4.2, so he sends a CR to cadence.
What's more, the expert finds that Cte engine doesn'tfalsephilewar2005-10-04T00:15:00+08:002005-10-03T16:37:06Z2005-10-03T16:37:06Ztag:blogger.com,1999:blog-5796168.post-112835742693910690Summary for Week 538 and 539I spent last two week in Zurich, working on timing constraints translation. I should translate a PKS tcl script to a simple SDC format which can work well with pks, encounter, primetime and even nanoroute. When I finish one or two lines, I will put them in pks, encounter and primetime to cross check compatiblity. The subset supported by pks, encounter and primetime simultaneously is quite limited.falsephilewar2005-09-16T22:19:00+08:002005-09-16T14:57:01Z2005-09-16T14:56:13Ztag:blogger.com,1999:blog-5796168.post-112688257388877232Week 537 SummaryIt's a fruitful week, though I almost did nothing in Monday. We had a meeting that day which made me quite tired. Tuesday I performed netlist translation, clock tree and buffer tree remove and formal check on a small module. Then another engineer will be able to floorplan. Since Wednesday I did timing constraints translation and business trip preparation in parallel. Yes, I will take a businessfalsephilewar2005-09-09T23:31:00+08:002005-09-09T15:42:46Z2005-09-09T15:42:46Ztag:blogger.com,1999:blog-5796168.post-112628056634054309Week 536 SummaryThis week I stuck in timing constraints translation. I have constraints for PKS written in tcl. However, new project will use encounter instead of PKS. Yes, you say, encounter and PKS are both from Cadence, why not read pks scripts directly to encounter? In cadence documents they recommend rewriting pks scripts in SDC format. Before rewriting, I have to be sure those PKS constraints do notfalsephilewar2005-09-03T15:10:00+08:002005-09-03T07:12:54Z2005-09-03T07:12:54Ztag:blogger.com,1999:blog-5796168.post-112573157460269313Resource Sharing 535Links from my furl page: Electronic Business - Success by design - 9/1/2005 - Electronic Business - CA6252392 #EETimes.com - Startup introduces 'analog virtual prototyping' #'The Man Behind the Microchip': The Next Small Thing - New York Times # EETimes.com - Partners release first detailed specs for Cell microprocessor #Electronic News - To the Power of 10 - 8/23/2005 - Electronic News -falsephilewar2005-09-03T14:58:00+08:002005-09-03T07:07:57Z2005-09-03T07:05:55Ztag:blogger.com,1999:blog-5796168.post-112573115530504324Week 535 SummaryI find little to talk about this week which is another quick-pass-week.
What I did:
Finalize visa application, then I am able to enter CH. Finish design flow proposal draft 0.7 based on review from Shalini. Start to remap version C netlist. Work on timing constraints translation. Help new colleague into the project.
What I should do next week:
Finish point 3 above.
Look forfalse