Thursday, September 14, 2006

Script to fix random number suffix generated by RC uniquify

If you are a reader of John Cooley's DeepChip, you must be familiar with the slogan that "It's not a BUG; it's a FEATURE!". Neither do I think it's a bug that RTL Compiler adds five- or six-digit random number suffixes to module names during uniquify and there must be good reasons for C company to do so.
It's fine with me, but not fine with our DfT tool. Our aged DfT tool needs a fixed list of bistshells and clock gating cells and can't work even one module name is changed. Instead of bistshell_32898 and bistshell_236840, bistshell_0 and bistshell_1 are more preferred.
Previously I fix the names by sed script that is too time consuming as module names inscrease, so I ask for a RC script from C Company. I received a script yesterday, played with it and wrote a new one this afternoon.
It's very simple. You can modify and redistribute it freely. Please notice that the scripts is provided "as is". I have tested it with one big subdesign, However, as an IC designer, I have to reminde that YMMV, :P

Download: change_uniq_name.tcl
Usage: after uniquify and map, source the script in rc and call procedure "change_uniq_name".
Suggest: At the first time, comment line 63 "mv $module_name ${x}_${count}" and redirect output to a log file. The file will list both original name and target name of every module that will be modified. Please Check it carefully. If everything is OK, uncomment and go!

posted by philewar @ 9/14/2006 10:21:00 PM 0 comments

Tuesday, September 12, 2006

An Issue Has Been Resolved

It's quite normal that top semiconductor companies may have their own CAD tools and it's also normal that they may find in-house tools are not as good as those from the Four Big Players. As a result, they start to phase out in-house tools.
Unfortunetely, my project employs one in-house tool that is being phased out and limitedly supported. The tool, I won't disclose its name, will swallow the netlist I synthesizing. When it suffers dyspepsia, it's my reponsibility to generated something more digestible. Yes, I even ask help for C company. After one week's trying and retrying, dividing and debugging, the issue resolves eventually. As it turns out, the root cause is that a switch of this in-house is mis-set. I don't mean to complain. Everybody will make mistakes. I also make supid mistakes, putting my efforts at vain.
Whatever, I have learnt advance usage of a synthesis tool from C company in the past week. Well, I bet you know what it is, :)

posted by philewar @ 9/12/2006 09:02:00 PM 2 comments

Saturday, March 18, 2006

IC design will follow pc-board design

This EDN article describes a law that "everything that happens in IC design, happened in pc-board design many years ago." I quite buy into this idea, because many times I introduce "system on a chip" concept to people, I show them PCB, as the definition of original system.

posted by philewar @ 3/18/2006 07:46:00 PM 0 comments

Tuesday, February 07, 2006

A Breakthrough in RFID

An article I read today from eetims talks about Philips has successfully presented a PLASTIC RFID chip. The prototype is at 13.56Mhz, which is said to be a dominant one. Yes, the chips inside our transportation smart card commnuicate with reader at 13.56Mhz.
For myself, once upon a time I was involved a project related to RFID. So I am quite excited by this news.

posted by philewar @ 2/07/2006 09:01:00 PM 0 comments

Monday, January 30, 2006

Happy Chinese New Year!

I have not blogged for almost one month, which doesn't mean I stop working on IC Design, :)
In first two weeks of January, we are busy to close our projects. And, max transition violations are recovered and fixed. Then I find it's fixed only in worst case, in best case I have another huge amount of violations. It seems encounter will not fix them automatically. I don't know the reason clearly. Whichever operating condition it is under, encounter will load worst lib. After the project close, the focus shift to learning. My topic is low power design, very interesting.

I think of what to blog here and simply my work won't arouse your attention so I plan to write sth. general and industy-news oriented. I really dont want to make you bored.

Finally, happy chinese new year to all!

posted by philewar @ 1/30/2006 12:17:00 PM 1 comments

Tuesday, December 27, 2005

Week 551 and 552 Summary

Happy Holiday! I think we finally achieve a closed timing before year end. When I left office 8PM today, there was only 5 hold violations in functional-mode-best-case-on-chip-variation (10% timing derate). No problems in test mode and in other corners of func mode. Last night I still had 150 hold violation paths in functional-mode-worst-case-on-chip-variation and this morning I found because pt memory is not cleared between different operating-condition-run. One remove_lib -all removed all hold violation in worst case ocv.
Tomorrow my vacation starts and wish I would not be called because of sucking timing, :)

posted by philewar @ 12/27/2005 10:09:00 PM 1 comments

Sunday, December 18, 2005

Week 550 Summary

Of coz this week we continue playing with place and route, static timing analysis. Last week it was found that timing arc to some output ports can not be reported by SOC Encounter and finally it turns out that encounter disables the timing arc when one pin of pad is tied to high/low. It really sucks. An old version of encounter can report but it crashes during sroute. That's why we upgrade. Besides that, timing looks better and better. Hopefully it will be fixed soon.

posted by philewar @ 12/18/2005 08:16:00 PM 0 comments

Sunday, December 11, 2005

Week 549 Summary

I went to company this afternoon and things were still not good. The bottleneck is timing constraints. As you may know, it comes from an old design in PKS tcl mode and I have translated it to sdc. The headache is FE only allows a subset of sdc, e.g. no edge from/to options and no invalid start/end points. -through has been used a lot, which causes other problems coz -through option in false paths and multicycle paths has a higher priority. Another problem is correlation between FE and PT. In our old design, there are two set of constraints, one for PnR, one for STA, both in PKS tcl. So I translate first set into sdc for FE, PKS and nanoruote and second set into PT-sdc for final timing sign-off. It's found that clock definitions in two sets are different. I really concern whether timing violation in PT will be recognized by FE or not. Whatever, we can't stop. To be an engineer means you have to trade-off, try and err, and get things done finally.

Talk about this week's news. First, Sun to open-source Niagara processor Verilog code. It's really big. UltraSPARC T1 is an 8-core processor. But in OpenSPARC I only find documents no verilog.
65nm is driving near and how can we survive? The trend is like what I thought before. Only application that kills. The only problem is not how many transistors you put in a single die. You will be at a break-even point that smaller gate length won't make money. It's of what function your one billion transistors perform. IC design will become intensive labour work and system architect will rule.

posted by philewar @ 12/11/2005 09:36:00 PM 1 comments

Friday, December 02, 2005

Week 548 Summary

Only four weeks are left ahead of tape-out and timing closure has not been achieved. Things are becoming better and better. We may get some fruits next week. I'm still working on STA. Definitely I learn quite a few of Primetime. As far as I see, setup violation may not be a big trouble but we might be killed by hold violation. Wish PKS could fix!

I wonder whether you know Deepchip.com and John Cooley or not. Recently John has released a demo of Hercules, Synopsys' new physical verification throw-out and asked for feedback. Today I get another mail from John which includes links to demos of Mentor Calibre and Cadence Assura on Deepchip.com. All of this is caused by an angry call. :D, quite funny. With a good sense of humour, John!

Finally, I recommend a good reading to you. The Lessons of History, from blog SOC Design, talks about sth. of Bob Noyce. Bob Noyce would have been a Nobel Prize winner if he would live as long as Mr. Jack Kilby. It is really an inspring story.

So much for this week. Dark days can be expected next week, :P

posted by philewar @ 12/02/2005 09:07:00 PM 0 comments

Saturday, November 26, 2005

Week 547 Summary

Last week I talked that my first project was stopped due it was not attractive to market any more. My colleagues and I are still working hard. We target at a tape-out-quality GDS2 end of year and prove that this team is capable of doing very deep sub-micron multi-clock-domain design. The schedule looks a little tight so I go to company this afternoon and work 3 hrs. The job I plan to do today is more or less scripting things. Though it's not a product, BIST shell of memories require substitution. The deliverables of BIST shell have some multicycle paths constraints in pks tcl format and should be integrated into top level constraints in primetime sdc format. Translation and integration are not difficult but need time and patience. It's suitable for doing it in Saturday afternoon. After the translation and integration, I send the script to primetime but to find some errors. Yes, due to BIST shell replacement, original constraints should be updated coz hierachy has changed. OK, I leave it for next Monday since it's almost 5PM. When I leave company, I feel quite good. I have not wasted time but headed to the aim. What a day!

posted by philewar @ 11/26/2005 08:11:00 PM 2 comments

Sunday, November 20, 2005

Week 546 Summary

After setting up clock tree synthesis, I finish final sta setup this week. Next week I am able to run full chip STA to further debug the quality of my constraints. It seems we are progressive towarding tape-out.
However, Mgmt had a tele-conference with us on Friday. The message was clear that my first project most probably would not be a production. Oh! What a pity! Anyway, it's business and it's life. I should always look at the bright side. I will continue working hard as if it was a one-million product. And maybe next project I can do some RTL and even spend some time again in Europe for architecture training, :D Well, even my dream doesn't come true. The new project in rumour is still gorgeous and attractive for me.

posted by philewar @ 11/20/2005 12:08:00 PM 0 comments

Sunday, November 13, 2005

Week 545 Summary

I just wonder whether you are bothered or not if I am keeping talking with my routine work. In the past week I was playing with ckSynthesis from Encounter. I have limited experiences on clock tree refinement and also dont know how to evaluate QoR. However, there are some basic principles. I think and perpare to evaluate by STA, which is next week's task.
On Friday I go to Cadence Shanghai to participate a workshop of First Encounter GPS. The focus is of hierachical design which is several million instances design containing hundreds of hard macros. Such scenario looks far away now but I think we will approach it sooner or later. I also take this opportunity to discuss with the lecturer on clock tree generation. Quite fruitful.

posted by philewar @ 11/13/2005 08:24:00 PM 0 comments

Friday, November 04, 2005

Week 544 Summary

This week I am into clock tree synthesis. As I mentioned last week, I have went through some documents. My job is more or less following the clock tree structure in old design and building one in our new design. As a very novice to encounter, I made stupid mistakes but got it done finally. Before I left office today, I found a big problem that six important clock subtrees are not generated. So I will investigate it next week.
Mr. CTO will give us a town meeting next week and I might think of some questions to ask him. Do you have any ideas? One question is of the end of Moore's law. I wonder whether it's time to stop decrease the gate length and fortify system solution one chip can achieve. Also I am interested in Philips' view on future of RFID.
Let me back to project. I think I am still climbing the learning curve. Since it's my first real project and it's quite complicated, I have not done very well so far. I should spend time on thinking of it. I am really eager to do better and show my possiblity.

posted by philewar @ 11/04/2005 11:37:00 PM 0 comments

Monday, October 31, 2005

CTS requires a uniquified netlist

When I try to synthesize a clock tree this afternoon, Encounter refuse with an error message saying:
specifyClockTree Option : -clkfile encounter.cts
**ERROR: CTS requires a uniquified netlist before you can run clock synthesis.

Uniquified? Yes, encounter provide a standalone unix utility "uniquifyNetlist" to do so, and it needs encounter license to do so. Later it seems whenever you do eco, ipo and write out a netlist, you need to uniquify it before doing sth. further on it. My colleague tells the tool even uniquify the cell name! Quite weird, I don't how encounter represent the data in memory. Whatever, it should be kept in mind.

posted by philewar @ 10/31/2005 09:39:00 PM 0 comments

Saturday, October 29, 2005

Week 543 Summary

This week I have finished timing constraint translation and try getting into clock tree. To do so, I should go through ctpks documents, encounter clock tree synthesis documents and design flow documents. By reading old scripts, I have some ideas how clock tree structure is in wally. Next Monday I can see ctpks log and gain more inside thoughts.
On Thursday my group had an chance to talk to VP HR of my business unit. Well, it's impossible for me in last company. So, though I'm only with this company for four months, I feel very good. Because I am respected and trusted. Four months is still a short period, Mr. VP HR said maybe two or three years will tell you whether you are into the culture or not. OK, I can wait to that day.

posted by philewar @ 10/29/2005 05:33:00 PM 0 comments

Friday, October 21, 2005

Week 542 Summary

Now I am focusing on static timing analysis. As I have mentioned before, I have to translate PKS tcl scripts to a simple SDC one for encounter, PKS, nanoroute and Primetime. I am fighting all the way to get the right timing report and pads issue arises. So I shift my focus to reporting delay through the pads. I make mistakes and correct them later. I am sitting in front of LCD and thinking. I am writing quickly on Notepad. Finally, with the support from my colleague, I manage to report sth. makes sense. When facing the whole design which is a multi-clock-domain one, I am quite lost. However when the problem is only related to a small part, I am able to break through. That's a lesson I have learnt.
At the begining of this week, I am quite regretful I have wasted my time in previous company coz I learn too much but dont learn one thing in depth. Yes, a coin always has two sides. Now I think maybe I have wasted some time before, however, it's not the time to complain, but to ramp up.

posted by philewar @ 10/21/2005 10:31:00 PM 0 comments

Friday, October 14, 2005

Week 541 Summary

Timing constraints translation is almost finished. Now I begin to perform timing analysis and ... get a lot of problems. First of all I should clear the issues reported by check_timing. I will work on that topic next week.

Besides all backend design activities, I pass a test for CBIC ISO9001:2000 audit awareness promotion. There are 28 problems in total. Score 23 and above, you pass. At my first try, I score 14. Well it's not bad since I didn't read any documents yet. The day after, I spent an hour reading traning documents, quality manual and blah blah. Wow, I score 23 and pass!

When I try to re-test it and head to a full-mark, the entry link disappears :P

posted by philewar @ 10/14/2005 09:55:00 PM 0 comments

Thursday, October 13, 2005

New Solvnet Feature - CommandZone

Finally I re-activate my solvnet account. It has been suspended since my former company mail account is deleted(IT guy told me I could keep it as long as I wanted on Friday but I found they deleted it on Monday morning).
Whatever I'm back to Solvnet and find a new feature called CommandZone. It locates in the bottom-right of your browser, still in beta version. CommandZone has two functions. One is to search command description. Yes, that's why I login to solvnet. SOLD in my system malfunctions. It's quite convenient. Another is to compare commands accross different releases. This is quite important coz I do have ache with commands difference accross releases. The bad thing is that I don't whether Cadence sourcelink has a similar one or not. I will see it after my registration.
To Synopsys on CommandZone: Good job! But you should have done this earlier, :-P

posted by philewar @ 10/13/2005 09:51:00 PM 0 comments

Friday, October 07, 2005

Week 540 Summary

I only work one day this week and I have fighted with conflicts between synopsys tools and CAD systems most time in the day. Anyway CAD team is so great that they solve all the problems.

I read The Silicon Steamroller from Steve Leibson today and I quite disagree with him. The point is I don't know how he calculate and draw a conculsion that Chinese fabless design companies can already handle well over 50%. I won't change my idea unless it's clarified.

The last thing I'd like to talk is wildcard. I have to expand a constraint including wildcard to a explicit constraint. Wow, I get two thousand lines and have to put them in another file. However, it makes life easier for compatitable with simple SDC format.

posted by philewar @ 10/07/2005 09:40:00 PM 0 comments

Tuesday, October 04, 2005

A funny bug

NW's comment reminds me of a funny bug I found recently. I create a huge-period clock in a sdc file and feed it into encounter. Encounter replyes that the value is too large to convert and then it skips clock difinition. I report this problem to inner helpdesk and the expert reproduces the issue both in 4.1 and 4.2, so he sends a CR to cadence.
What's more, the expert finds that Cte engine doesn't complain it but Fe engine has the problem. Of coz, my period is a ms level which may seem ridiculous in today's deep submircon design. But, it's also funny to see encounter only use a short-length value representing clock period, :)

posted by philewar @ 10/04/2005 08:13:00 PM 2 comments

Summary for Week 538 and 539

I spent last two week in Zurich, working on timing constraints translation. I should translate a PKS tcl script to a simple SDC format which can work well with pks, encounter, primetime and even nanoroute. When I finish one or two lines, I will put them in pks, encounter and primetime to cross check compatiblity. The subset supported by pks, encounter and primetime simultaneously is quite limited. Some edge options have to be translated in another way with understandings of design, which is the most difficult for me coz I do understand a little of design. So I will continue working on this after long national holiday.

When I was in Zurich, I met a backend guy who would leave company soon and asked me whether I was prepared for backend or not. He said people doing several yrs of backend would transfer to other positions like front end and his next position is of RTL. I did not answer him, coz I have thought about the same problem already but without any good solutions.

Plan is always catching up with Change but fails. I will see what opportunity comes and try to grasp. But now I'd better enjoy the holiday and release my jet lag.

posted by philewar @ 10/04/2005 12:15:00 AM 2 comments

Friday, September 16, 2005

Week 537 Summary

It's a fruitful week, though I almost did nothing in Monday. We had a meeting that day which made me quite tired. Tuesday I performed netlist translation, clock tree and buffer tree remove and formal check on a small module. Then another engineer will be able to floorplan. Since Wednesday I did timing constraints translation and business trip preparation in parallel. Yes, I will take a business trip to Zurich since tomorrow. I wish everything goes fine, not only me but my paofu as well.

I'd like to speak sth. about clock tree and buffer tree removal in first encounter.
To remove clock tree, you have to
1. setup the database: read design in verilog, lef, lib, sdc(define clock root, IMPORTANT!!!) or equivalent things;
2. do a rough floorplan, place area/io;
3. Specify clocktree;
4. deleteClockTree.
To remove buffer tree, you have to
1. prepare a file listing buffer tree root(port or net, I didn't try with pin);
2. deleteBufferTree -selnetfile (the file you creating in step 1)
It's not a normal usage of these two commands. I have to do this because only post layout netlist is available.

Go go go, Chenbo!

posted by philewar @ 9/16/2005 10:19:00 PM 0 comments

Friday, September 09, 2005

Week 536 Summary

This week I stuck in timing constraints translation. I have constraints for PKS written in tcl. However, new project will use encounter instead of PKS. Yes, you say, encounter and PKS are both from Cadence, why not read pks scripts directly to encounter? In cadence documents they recommend rewriting pks scripts in SDC format. Before rewriting, I have to be sure those PKS constraints do not mal-function. So I set up the environment, read design, apply constraints and generate reports. Wow, I get unconstrained paths! What's the hell it come? Finally I identify it's caused by command options variation between different PKS version. I almost spend two or three days on it and make little advance. This afternoon, I make a disicion that I will translate the constraints directly. The evaluating method is comparing encounter reports with those reports generated in ZRH. Go for next week!

posted by philewar @ 9/09/2005 11:31:00 PM 1 comments